1. Field of the Invention
The present invention relates to a flash memory device, and more particularly, to a method for fabricating a connection structure to electrically connect elements of a flash memory device.
2. Description of the Background Art
A flash memory, being a non-volatile memory device, can be composed of highly integrated components that allow repetitive data storage by electrically re-writing thereto. As such, a flash memory can be used instead of magnetic memory devices, such as a hard disk for various storage device applications.
In order to further increase the integration of a cell array in the flash memory, several methods have been employed, whereby various bit lines are arranged to be commonly used by a plurality of components. The so-called xe2x80x9cvirtual ground methodxe2x80x9d employs a drain line and a source line that are alternately used. The so-called xe2x80x9ccommon bit line common ground methodxe2x80x9d employs a single source line formed between two drain lines.
FIG. 1 depicts a connection structure between segment transistors and an array of memory cells in a flash memory device employing the common bit line common ground method in accordance with the conventional art. In FIG. 1, the cell array includes at least a first memory cell block B1 and a second memory cell block B2, both having the same structure and connected together symmetrically. It can be understood that additional memory cell blocks having identical configurations may be further connected to achieve the overall cell array configuration. Only two memory cell blocks are depicted for the sake of brevity in explaining the features of a conventional memory cell array.
In the first memory cell block B1, the gate electrodes xe2x80x98Gxe2x80x99 of each transistor in a memory cell xe2x80x98Mxe2x80x99 within the same array row are connected to a common cell word line 18. The sources xe2x80x98Sxe2x80x99 of each transistor in a memory cell xe2x80x98Mxe2x80x99 within the same array column are connected to a common source CS. Here, two adjacent transistors in two adjacent memory cells xe2x80x98Mxe2x80x99 of the same array row are configured such that their sources are connected together. The common source CS is also connected with a source line 19, so that the same signal is applied to all the common sources CS in the first memory cell block B1. The drains xe2x80x98Dxe2x80x99 of each transistor in a memory cell xe2x80x98Mxe2x80x99 within the same array column are connected to a common bit line 15a. Each common bit line 15a has an end portion 17a. 
The first memory cell block B1 further comprises a segment transistor 6a for each array column. Each segment transistor 6a has a source 10a connected with the end portion 17a of the common bit line 15a, a drain 12a connected with a data line 14, and a gate electrode xe2x80x98Gxe2x80x99 connected with a common cell block word line 7a. 
The second memory cell block B2 has the same configuration as the first memory cell block B1, and is connected to the first memory cell block B1 in a symmetrical and mirror-image manner. Namely, the drains of the segment transistors 6a at the end of the memory array columns of the first memory cell block B1 are connected to the drains of the segment transistors 6b at the end of the memory array columns of the second memory cell clock B2 via the data line 14 between the memory cell blocks B1, B2. The gate electrodes of the segment transistors 6b are connected to a common block word line 7b. The second memory block B2 also has common bit lines 15b connecting the drains of the transistors in memory cells of the same array column.
A conventional method for fabricating a connection structure (indicated as region xe2x80x98Axe2x80x99 in FIG. 1) between the segment transistors 6a, 6b and the memory cell blocks B1, B2 of the flash memory device in accordance with the conventional art will now be described with reference to FIGS. 2A through 4C.
FIGS. 2A through 2D are cross-sectional views showing a series of processes for fabricating common bit lines and memory cells of the flash memory device in accordance with the conventional art.
FIGS. 3A through 3C are cross-sectional views showing a series of processes for fabricating elements of the memory cells prior to forming the segment transistors of the flash memory device in accordance with the conventional art.
FIGS. 4A through 4C are cross-sectional views showing a series of processes for fabricating a connection structure between the segment transistors and the memory cells of the flash memory device in accordance with the conventional art.
As shown in FIG. 2A, after a first oxide film 21 is formed on the upper surface of a substrate 20, a first polysilicon layer 22 is formed at a portion where segment transistors are to be formed on the upper surface of the first oxide film 21. Then, an arsenic (As) or phosphorus (P) type impurity is ion-implanted into portions of the substrate not covered by the first polysilicon layer 22.
Thereafter, as shown in FIG. 2B, a diffusion process is performed at a high temperature to create an impurity diffusion layer on portions of the substrate not covered by the first polysilicon layer 22, to thus form the common bit lines 15a and 15b also shown in FIG. 1. A buried oxide film 21b is then formed on the common bit lines 15a, 15b. 
Subsequently, as shown in FIG. 2C, a second oxide film 23 is deposited on the upper surface of the buried oxide film 21b by photolithography and selective etching. Here, if no misalignment or over-etching occurs during the photolithography or the etching process, the second oxide film 23 is accurately aligned on top of the buried oxide film 21b. However, if misalignment occurs during the photolithography or the etching process, the common bit lines 15a or 15b may be disconnected from the first oxide layer 21. As an example, FIG. 2D shows the common bit line 15b of the second memory cell block B2 being disconnected from the first oxide layer 21 due to misalignment during the photolithography and/or etching process.
Thereafter, as shown in FIG. 3A, a second polysilicon layer 24 is formed over the entire misaligned structure, and as shown in FIG. 3B, a second polysilicon pattern 24a is formed on the upper surface of the first polysilicon layer pattern 22 by performing photolithography and etching processes. Then, as shown in FIG. 3C, an insulation film 29 is formed on the upper surface of the second polysilicon layer pattern 24a and overlapping a portion of the second oxide film 23. Subsequently, a word line 28 for each memory cell block is formed on a portion of the second oxide film 23. This completes the conventional fabrication method of memory cell blocks, which will then be connected with segment transistors.
Thereafter, as shown in FIG. 4A, a photoresist 30 is formed over the word lines 28 by photolithography, while the insulation film 29, the second polysilicon layer pattern 24a, the first polysilicon layer 22, and the first oxide film 21 are all removed by etching.
However, referring back to FIG. 2D, because the second oxide film 23 was misaligned with the first polysilicon layer 22, the junction portions 27a and 27b of the memory cell blocks shown in FIG. 4A formed upon etching the insulation film 29, the second polysilicon layer pattern 24a, the first polysilicon layer 22, and the first oxide film 21, do not have the proper configuration. As such, the segment transistors to be subsequently formed between the memory cell blocks will not be properly connected with the common bit lines 15a and 15b of each memory cell block, as will be explained hereafter.
As shown in FIG. 4B, a third oxide film 33, acting as a gate oxide film, is deposited on the upper surface of the substrate 20 between the junction portions 27a and 27b of the memory cell blocks. Gate electrodes 31a and 31b are then respectively formed on the third oxide film 33. Then, insulating side wall spacers 32 are formed at the sides of the gate electrodes 31a and 31b. Subsequently, an impurity is ion-implanted into the semiconductor substrate 20 at both sides of and between the gate electrodes 31a and 32b, and is diffused to form sources 37a, 37b and a common drain 38. Thus, the segment transistor 6a properly connected with the first memory cell block B1 of FIG. 1 comprises gate electrode 31a, source 37a and common drain 38, while the segment transistor 6b not properly connected with the second memory block B2 comprises gate electrode 31b, source 37b and common drain 38.
Thereafter, as shown in FIG. 4C, a planarization layer 34 is deposited over the resulting structure on the substrate as shown in FIG. 4B. The planarization layer 34 is then selectively etched to form a contact hole 35 exposing the upper surface of the common drain 38. Then, a metal 36 is formed in the contact hole 35 and on a portion of the planarization layer 34 to cover the contact hole 35, to thereby complete the formation of and connection between the segment transistors 6a, 6b and the memory cell blocks in the conventional flash memory device.
However, the conventional method of formation and connection between the segment transistors and the memory cell blocks in the conventional flash memory device have some problems. Process misalignment during fabrication causes improper electrical connections between the segment transistors and the memory cell blocks as explained with regard to FIGS. 2A through 4C above. As such, a process margin between the segment transistors and the common bit lines needs to be established during fabrication to allow for a margin of error and to take into consideration any possible misalignment during fabrication. However, the provision of process margins undesirably increases the overall footprint or required area of the flash memory device.
The present invention provides a method for fabricating a connection structure between a segment transistor and a memory cell of a flash memory device, allowing precise electrical connections therebetween to thus improve flash memory product reliability.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described herein, a method for fabricating a connection structure between a segment transistor and a memory cell of a flash memory device includes the steps of: forming a first gate oxide film on the upper surface of a semiconductor substrate having a segment transistor region and a memory cell region; forming gate electrodes for a segment transistor on the first gate oxide at the segment transistor region; forming a photoresist pattern on the first gate oxide film of the memory cell region; ion-implanting a first impurity into the semiconductor substrate at the segment transistor region by using the gate electrodes of the segment transistors as a self-alignment mask, to form a first source and a first drain for the segment transistor; and ion-implanting a second impurity on the whole surface of the semiconductor substrate by using the gate electrode of the segment transistor as a mask, to form a common bit line and a common source inside the semiconductor substrate of the memory cell region, and simultaneously forming a second source and a second drain below the first source and below the first drain of the segment transistor, respectively.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.